This application claims the priority benefit of Taiwan application Ser. No. 92103363, filed Feb. 19, 2003.
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a flash memory device.
2. Description of Related Art
Flash memory is a data storage device. Data within the flash memory can be accessed, read and erased multiple of times. Moreover, data within the device is retained even after power to the device is turned off. With these advantages, flash memory has become one of the most widely adopted non-volatile memories inside a personal computer and electronic equipment.
A typical flash memory device has a polysilicon floating gate and a polysilicon control gate above the floating gate. The control gate and the floating gate are separated from each other by a dielectric layer and the floating gate and the substrate are separated from each other by a tunneling oxide (the so-called stack gate flash memory). A positive or a negative voltage is applied to the control gate of the flash memory device to control the injection of charges into the floating gate or the discharge of charges trapped inside the floating gate.
FIGS. 1A to 1D are schematic cross-sectional views showing some of the steps for producing a conventional flash memory device. The substrate 100 in FIGS. 1A to 1D can be divided into a memory cell region 102 and a peripheral circuit region 104. As shown in FIG. 1A, a plurality of isolation structures 106 for marking out the active regions is formed in the memory cell region 102 and the peripheral circuit region 104. Thereafter, a tunneling dielectric layer 108 is formed over the substrate 100 in the memory cell region 102 and a liner layer 110 is formed over the substrate 100 in the peripheral circuit region 104. A conductive layer 112 is formed over the entire substrate 100. The conductive layer 112 over the memory cell region 102 is patterned to form a plurality of longitudinal lines 112a. A gate dielectric layer 114 is formed over the substrate. The gate dielectric layer 114 can be a composite layer such as an oxide/nitride/oxide (ONO) layer.
As shown in FIG. 1B, a patterned photoresist layer 116 is formed over the substrate 100. The patterned photoresist layer 116 covers the memory cell 102 but exposes the peripheral circuit region 104. Using the patterned photoresist layer as a mask, the gate dielectric layer 114 and the conductive layer 112 above the peripheral circuit region 104 is removed. Thereafter, a gate dielectric layer 118 and another gate dielectric layer 120 having a thickness greater than the gate dielectric layer 118 is formed over the peripheral circuit region 104.
As shown in FIG. 1C, the patterned photoresist layer 116 is removed and then another conductive layer 122 is formed over the entire substrate 100.
As shown in FIG. 1D, the conductive layer 122 is patterned to form a control gate conductive layer 124 in the memory cell region 102. The gate dielectric layer 114, the conductive layer 112a and the tunneling dielectric layer 108 are patterned to form a stacked gate structure 126. Meanwhile, the conductive layer 122 on the patterned peripheral circuit region 104 to form a gate structure 128.
In the aforementioned fabrication process, the gate dielectric layer 114 is a very thin and fragile film. Consequently, the gate dielectric layer 114 is easily damaged (for example, in the ashing process of the patterned photoresist layer 116 or cleaning process). Any deviation in the properties of the gate dielectric layer 114 is likely to bring about some deterioration in the data retaining capacity of the flash memory.
Accordingly, one object of the present invention is to provide a method of fabricating a flash memory device capable of reducing in-process damage to the gate dielectric layer within the flash memory and hence boosting overall device performance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating flash memory. A substrate divided into a memory cell region and a peripheral circuit region is provided. A first conductive layer is formed over the substrate and then the first conductive layer in the memory cell region is patterned to form a first gate conductive layer. Thereafter, a gate dielectric layer is formed over the substrate. A second conductive layer and a passivation layer are sequentially formed over the gate dielectric layer. The passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region are removed and then a third conductive layer is formed over the substrate. The third conductive layer and the passivation layer in the memory cell region are removed. After that, the second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region is patterned to form a plurality of memory gates. Finally, the third conductive layer in the peripheral circuit region is patterned to form a plurality of gates.
In this invention, after removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region but before forming the third conductive layer over the substrate, further includes a plurality of oxide layers each having a different thickness in the peripheral circuit region.
After removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region but before forming the third conductive layer over the substrate, this invention may further include forming at least one first gate dielectric layer and a second gate dielectric layer in the peripheral circuit region. The step of forming the first gate dielectric layer and the second gate dielectric layer in the peripheral circuit region is conducted before forming the patterned photoresist layer in the peripheral circuit region. The patterned photoresist layer exposes the region for forming the first gate dielectric layer. Thereafter, an implant is carried out implanting dopants into the region for forming the first gate dielectric layer. After removing the patterned photoresist layer, a thermal oxidation is carried out to form the first gate dielectric layer and the second gate dielectric layer in the peripheral circuit region.
In this invention, a conductive layer and a passivation layer are sequentially formed over the gate dielectric layer in the memory cell region after forming the gate dielectric layer. Hence, the gate dielectric layer is protected against any harmful in-process damages so that properties of the gate dielectric layer can be maintained.
Furthermore, the stack gate structure in the memory cell region and the gate structure in the peripheral circuit region have different thickness. Hence, coupling capacitance between the word lines and the bit lines can be optimized.
In addition, the control gate conductive layer in the memory cell region has a thickness greater than the gate structure in the peripheral circuit region. Thus, in the process of patterning the second conductive layer to form the control gate conductive layer and the subsequent patterning of the gate dielectric layer, the first conductive layer, the tunneling dielectric layer to form the stack gate structure, the third conductive layer in the peripheral circuit region is also concurrently patterned to form the gate structure. This simplifies the overall processing steps considerably.
This invention also provides an alternative method of fabricating flash memory. A substrate divided into a memory cell region and a peripheral circuit region is provided. A first conductive layer is formed over the substrate. The first conductive layer in the memory cell region is patterned to form a first gate conductive layer. Thereafter, a gate dielectric layer is formed over the substrate. A second conductive layer is formed over the gate dielectric layer. After removing the second conductive layer and the first conductive layer in the peripheral circuit region, a third conductive layer is formed over the substrate. The second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region is patterned to form a plurality of memory gates. The third conductive layer in the peripheral circuit region is patterned to form a plurality of gates.
In this invention, after removing the second conductive layer and the first conductive layer in the peripheral circuit region but before forming the third conductive layer over the substrate, further includes forming a plurality of oxide layers each having a different thickness over the peripheral circuit region.
After removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region but before forming the third conductive layer over the substrate, this invention may further include forming at least one first gate dielectric layer and a second gate dielectric layer in the peripheral circuit region. The step of forming the first gate dielectric layer and the second gate dielectric layer in the peripheral circuit region is conducted before forming the patterned photoresist layer in the peripheral circuit region. The patterned photoresist layer exposes the region for forming the first gate dielectric layer. Thereafter, an implant is carried out implanting dopants into the region for forming the first gate dielectric layer. After removing the patterned photoresist layer, a thermal oxidation is carried out to form the first gate dielectric layer and the second gate dielectric layer in the peripheral circuit region.
In this invention, a conductive layer is formed over the gate dielectric layer in the memory cell region after forming the gate dielectric layer. Hence, the gate dielectric layer is protected against any harmful in-process damages so that properties of the gate dielectric layer can be maintained.
Furthermore, the stack gate structure in the memory cell region and the gate structure in the peripheral circuit region have different thickness. Hence, coupling capacitance between the word lines and the bit lines can be optimized.
In addition, the control gate conductive layer in the memory cell region has a thickness greater than the gate structure in the peripheral circuit region. Thus, in the process of patterning the second conductive layer to form the control gate conductive layer and the subsequent patterning of the gate dielectric layer, the first conductive layer, the tunneling dielectric layer to form the stack gate structure, the third conductive layer in the peripheral circuit region is also concurrently patterned to form the gate structure. This simplifies the overall processing steps considerably.
This invention also permits the absence of the passivation layer so that the second conductive layer directly serves as a protective layer for the gate dielectric layer. This simplified the fabrication process of the flash memory even more.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.